1. Field
Example embodiments relate to a method of manufacturing a semiconductor device. More particularly, example embodiments relate to a method of manufacturing a semiconductor device having a metal silicide layer.
2. Description of the Related Art
Semiconductor devices commonly employ switching devices such as a metal-oxide semiconductor (MOS) transistors. As the degree of integration of semiconductor devices continues to increase, the size of MOS transistors continues to decrease. Accordingly, the channel length of the MOS transistor is reduced, and, as a result, the occurrence of the short channel effect is more likely. Also, the resulting width of a gate electrode may be reduced due to the reduction of the channel length of the MOS transistor. As a result, the electrical resistance of the gate electrode may be increased.
A silicidation process for decreasing the electrical resistance of semiconductor devices is widely employed. Generally, the silicidation process in which a metal silicide layer is selectively formed on a gate electrode and a source/drain region helps to offset increase in the electrical resistances of the gate electrode and the source/drain contacts. Recently, various metal materials such as cobalt, nickel, etc. have been used in the silicidation process. However, because cobalt and/or nickel are to be formed in a thin layer when used as a silicide layer, these configurations have encountered processing difficulties.
The electrical resistance of the gate electrode and the source/drain region can have an effect on the resulting transmission speed of electrical signals in semiconductor devices. The transmission speed also can be related to the mobility of electric charge in the gate channel region. In recent research, it has been determined that when stress is applied to the channel region, the transmission speed of the transistor can be increased. Accordingly, a method of applying stress to the channel region has been developed in which a structure that generates stress on the gate electrode or the active region is provided.
FIG. 1 is an electron microscope image of a conventional gate structure.
Generally, a gate spacer encloses sidewalls of a gate electrode. When the gate spacer encloses a sidewall of a gate electrode, stress is not concentrated on the channel region of the gate structure, but instead is also distributed to other regions. Thus, the gate spacer can be removed according to some methods of manufacturing a semiconductor device as shown in FIG. 1. However, when the gate spacer is removed by a dry etching process, the active region may be attacked by the etch, causing the source/drain region to become over-etched, which can result in junction leakage during operation, and therefore reducing device performance. Particularly, in a method in which a gate spacer on a sidewall of a gate electrode is sufficiently removed to obtain a stress layer effect, sufficient etching is required to remove the gate spacer. In this case, an active region can become over-etched during removal of the gate spacer, and device performance can be thereby limited.